1. Field of the Invention
2. Description of the Related Art
The design and manufacture of semiconductor devices continues to improve and produce semiconductor devices having higher operating speeds and larger storage capacities. In order to expand upon the current generation of semiconductor devices, efforts are continuing to develop improved designs and processes for increasing density, improving reliability, reducing cost and/or reducing response time.
Integrated circuits are typically manufactured by forming large numbers of transistors, capacitors and other circuit elements on a single substrate. The various transistors and other elements are then electrically interconnected using one or more patterns of conductive material, typically a metal, to achieve the desired circuit function(s). Metal oxide semiconductor (MOS) and bipolar VLSI and ULSI devices, for example, tend to include multilevel interconnection structures by which millions of individual transistors are interconnected to produce, for example, DRAM and SRAM devices. During the process of forming such multilevel interconnection structures, the surface of the top layer tends to become increasingly irregular and uneven as the circuit elements and interconnection patterns are formed.
For example, a semiconductor wafer having metal interconnection layers is typically manufactured by forming the underlying circuit elements and then depositing a first insulating layer over the circuit elements. Contact holes are then opened in certain regions of the first insulating layer to permit electrical contact to be made to certain regions of the circuit elements. A first metal layer is deposited, patterned and etched to form a first metal pattern. Because the circuit elements tend to present an uneven surface topography, the surface of the first insulating layer formed over those elements will also tend to be uneven. If the first metal layer is formed directly on an uneven first insulation layer, however, the metal layer may tend to exhibit various defects such as thinning or fractures as a result of protrusions and openings present in the underlying insulation layer.
Similarly, when one or more additional conductive patterns are utilized, one or more insulating layers will be formed over the underlying conductive pattern and will tend to exhibit, at least initially, surface roughness reflecting the underlying conductive pattern. If a second metal layer is formed directly on an uneven insulating layer, the second metal layer may also tend to exhibit various defects such as thinning or fractures as a result of the varied topography of the underlying insulation layer.
Because defects in any of the metal patterns will tend to depress both the yield and the reliability of the resulting semiconductor devices, conventional semiconductor processes tend to include planarization steps to produce a relatively planar surface on the insulating layer before forming the contact or via openings or depositing the conductive layers. When more than one metal interconnection layer is used, the insulating layers formed between successive metal layers may be planarized and thereby improve the uniformity of the metal layer and reduce defects in the resulting metal pattern.
A variety of materials may be utilized as the insulating layer, including, for example, HDP (high-density plasma) CVD oxide layers, O3-TEOS (ozone-tetraethylorthosilicate), for filling the trench openings in shallow trench isolation (STI) processes or as an insulating interlayer material arranged between conductive layers. However, these types of oxide layers tend to exhibit poor gap-filling characteristics, e.g., a layer having bridges, gaps and voids, when the structures being coated have feature sizes consistent with design rules such as those for 0.13 μm and sub-0.10 μm devices.
Various methods have been developed for providing a planarized insulation layer including reflow processes utilizing a borophosphosilicate glass (BPSG) layer, coating processes utilizing a SOG layer and chemical mechanical polishing (CMP) processes for removing material from the wafer surface.
Although BPSG has been utilized as an insulation layer material for filling gaps between the lines in conducting wire, the nature of the deposited BPSG film may depend primarily on highly equipment-specific deposition parameters. In addition, gases used in the BPSG deposition process are expensive and severely toxic and, once deposited, the BPSG layer requires a high-temperature reflow process to achieve a more planarized surface. Further, compared with other oxides, BPSG tends to exhibit a higher etch rate in wet etchants, such as HF or BHF solutions, thereby complicating control of the etch process.
As the device packing density increases and the design rule sizing decreases for memory devices having capacities on the order of 256 megabits or more, BPSG insulation layers may tend to exhibit increased numbers of defects, such as voids and bridges, that tend to reduce device yield and reliability. Further, although an etch stop layer may be used to address etch selectivity issues, the formation of the BPSG layer may damage the etch stop layer and the additional layer results in increased process complexity. As a result, conventional BPSG processes typically utilize a thermal reflow process and/or a CMP process to produce a sufficiently planar surface.
An alternative to the BPSG processes are those processes that form an insulation layer by spin-coating a SOG composition to form a generally planar SOG layer on the underlying structures. For example, U.S. Pat. No. 5,310,720 (issued to Shin et al.) discloses a method in which a polysilazane layer is formed using a SOG composition and then heated in an oxygen atmosphere to form a silicon oxide layer. U.S. Pat. No. 6,479,405 (issued to Lee et al.) discloses a method of forming a silicon oxide layer through heat treatment of a SOG layer including PHPS. U.S. Pat. No. 5,976,618 (issued to Fukuyama et al.) discloses a method in which an inorganic SOG layer is formed and then subjected to a two-step heat treatment process to convert the SOG layer into a silicon oxide layer. Korean Patent Laid-Open Publication No. 2002-45783 discloses a method of forming a SOG layer on a substrate, pre-baking the SOG layer at 50° C. to 350° C. to remove solvent from the SOG layer, hard-baking the SOG layer at 350° C. to 500° C. to reduce the generation of particles, and then annealing the SOG layer at 600° C. to 1200° C. to form an oxide layer. The disclosures of each of the documents referenced above are incorporated by reference herein in their entirety.
U.S. Pat. No. 5,494,978 (issued to Shinizu et al.) discloses a method of preparing a defoamed polysilazane utilizing inorganic polysilazane having an average molecular weight of 100-100,000. U.S. Pat. No. 5,905,130 (issued to Nakahara et al.) discloses a methods of preparing polysilazane by i) reacting a polyaminosilane compound with a polyhydrogenated nitrogen-containing compound in the presence of a base catalyst or by ii) reacting a polyhydrogenated silicon compound with a polyhydrogenated nitrogen-containing compound under a basic solid oxide catalyst. U.S. Pat. No. 5,436,398 (issued to Shimizu et al.) discloses a method of preparing PHPS having an average molecular weight of about 1,120. U.S. Pat. No. 4,937,304 (issued to Ayama et al.) and U.S. Pat. No. 4,950,381 (issued to Takeuchi et al.) discloses methods for preparing polysilazanes having a range of molecular weights. The disclosures of each of the documents referenced above are incorporated by reference herein in their entirety.
The basic backbone structure of polysilazane-based SOG materials includes Si—N, Si—H and N—H bonds. When such materials are heated to a sufficient temperature under the proper atmosphere, typically including oxygen and water vapor, a majority of the Si—N bonds will be converted into (or substituted with) Si—O bonds. Thus a relatively simple spin coating process followed by a relatively simple thermal curing process may be utilized to form a SOG layer and then to convert the SOG layer into a silicon oxide layer in a relatively simple and economical manner.
Not all of the Si—N bonds, however, are converted to Si—O bonds (see, for example, Japanese Patent Laid-Open No. Hei 11-145286) during such a curing process. In order to convert substantially all of the remaining Si—N bonds to Si—O bonds, the cured SOG layer is typically then treated (or annealed) at a higher temperature (about 600° C. to 1200° C.) under an oxidizing atmosphere. When the SOG layer is treated at a temperature of about 300° C. to 600° C. the conversion of polysilazane in the SOG layer to silicon oxide (SiO2) tends to be incomplete, producing a layer with a less stable structure of SiHxNyOz (wherein x, y, z are positive numbers). Layers having this less stable structure will tend to continue to react with atmospheric oxygen and water vapor over time to convert the SiHxNyOz more completely to a SiO2 layer.
FIG. 1 is a Fourier Transform Infrared Spectroscopy (FTIR) graph illustrating the absorbance characteristics of a SOG layer both immediately after hard-baking and after the hard-baked SOG layer was maintained for an additional seven days under ambient conditions. The SOG layer was formed by depositing a SOG composition on a substrate to a thickness of about 3,400 Å. This deposited SOG layer was then hard-baked at a temperature of about 400° C. for period of between about 10 minutes and about 60 minutes under an oxygen atmosphere and the absorbance characteristics of the resulting layer were evaluated using FTIR. The substrate with the hard-baked SOG layer was then maintained under ambient conditions for seven days and the absorbance characteristics of the aged layer were again evaluated using FTIR. As reflected in FIG. 1, FTIR trace “a” was obtained immediately after the SOG layer had been hard-baked and FTIR trace “b” was obtained after the hard-baked SOG layer had been aged for seven days.
As can be observed by comparing the peaks of the traces illustrated in FIG. 1, immediately after the hard-baking step the SOG layer still clearly included minor components of N—H and Si—H bonds in addition to the majority Si—O bonds. However, after seven days the conversion of the less stable bonds N—H and Si—H to Si—O bonds had progressed to a degree that the N—H and Si—H peaks were substantially reduced.
FIG. 2A is a graph tracking the changes in the measured thickness (Å) and reflective index (R.I.) of a SOG layer over the course of about 24 hours and FIG. 2B is a similar graph tracking changes in thickness and R.I. for about a week. FIG. 3A is a graph tracking the changes in the measured etch rate of the SOG layer over the course of about 24 hours and FIG. 3B is a similar graph tracking the changes in the measured etch rate for about a week.
The SOG layer was formed by depositing a SOG composition on a substrate to a thickness of about 3,400 Å. This deposited SOG layer was then hard-baked at a temperature of about 400° C. for about 60 minutes under an oxidizing atmosphere, typically containing oxygen and/or water vapor. The R.I. and thickness of the SOG layer were then repeatedly measured to obtain the data presented in FIGS. 2A-B. In FIGS. 2A-B, the R.I. measurements are denoted by the symbol □ and the thickness measurements are denoted by the symbol ♦. The etch rate of the aging SOG layer was also repeatedly measured using a wet oxide etchant containing hydrogen fluoride (HF) under substantially constant etch conditions to obtain the data presented in FIGS. 3A-B for the purpose of examining the SOG etch rate as a function of the delay between the formation of the SOG layer and start of the wet etch.
As shown in FIGS. 2A-B and 3A-B, the R.I., thickness and etch rate of the SOG layer vary over time, thus complicating efforts to control the SOG etch process and increasing the chance of overetching or underetching such a SOG layer. Aging in oxidizing atmosphere may prevent such problems, but the aging takes long time to delay manufacturing process.